An approach for prognosis of manufacturing of comparator with account missmatch-induced stress. On increasing of density of elements

Abstract

In this paper we introduce an approach to increase density of field-effect transistors framework low-power dynamic comparator used in the far-end and near-end crosstalk adaptation loop. Based on this approach one shall manufacture a heterostructure with specific sections in epitaxial layer. These sections should be doped by diffusion or ion implantation. Doping procedure finishing by optimized annealing. During analysis of manufacturing of the considered comparator we find an approach for decreasing mismatch-induced stress. Also we consider an approach for analytical modeling of heat and mass transport during manufacturing of the considered comparator and other integrated circuits.